{"title":"实现1.6 NEF和2.56 PEF的脑机接口低噪声神经信号放大器","authors":"Weijian Chen, Xu Liu, Weisong Liang, Ze-Xi Lu, Peiyuan Wan, Zhijie Chen","doi":"10.1109/APCCAS55924.2022.10090394","DOIUrl":null,"url":null,"abstract":"This paper presents a low-power and low-noise front-end amplifier (FEA) dedicated to recording and preprocessing biomedical signals for brain-machine interface. The FEA employs a current-reused architecture which adopts an inverter-based differential input stage to achieve considerable $g_{m}/I$ efficiency and low noise. With a carefully designed common-mode feedback circuit, the output common-mode voltage of the fully-differential FEA is stabilized within an acceptable margin of error about 1 mV. All transistors in FEA operate in the sub-threshold region, realizing low power consumption. This current-reused FEA implemented in a CMOS 0.18- $\\mu \\mathbf{m}$ technology provides a noise efficiency factor (NEF) and power efficiency factor (PEF) of 1.6 and 2.56, respectively, corresponding to an input-referred noise of 2.37 $\\mu \\boldsymbol{V}_{rms}$. This FEA consumes only 2 $\\mu \\mathbf{A}$ current from 1 V supply and the active area is $0.2 \\ \\mathbf{mm} \\times 0.2$ mm.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Low-Noise Neural Signal Amplifier Achieving 1.6 NEF and 2.56 PEF for Brain-Machine Interface\",\"authors\":\"Weijian Chen, Xu Liu, Weisong Liang, Ze-Xi Lu, Peiyuan Wan, Zhijie Chen\",\"doi\":\"10.1109/APCCAS55924.2022.10090394\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a low-power and low-noise front-end amplifier (FEA) dedicated to recording and preprocessing biomedical signals for brain-machine interface. The FEA employs a current-reused architecture which adopts an inverter-based differential input stage to achieve considerable $g_{m}/I$ efficiency and low noise. With a carefully designed common-mode feedback circuit, the output common-mode voltage of the fully-differential FEA is stabilized within an acceptable margin of error about 1 mV. All transistors in FEA operate in the sub-threshold region, realizing low power consumption. This current-reused FEA implemented in a CMOS 0.18- $\\\\mu \\\\mathbf{m}$ technology provides a noise efficiency factor (NEF) and power efficiency factor (PEF) of 1.6 and 2.56, respectively, corresponding to an input-referred noise of 2.37 $\\\\mu \\\\boldsymbol{V}_{rms}$. This FEA consumes only 2 $\\\\mu \\\\mathbf{A}$ current from 1 V supply and the active area is $0.2 \\\\ \\\\mathbf{mm} \\\\times 0.2$ mm.\",\"PeriodicalId\":243739,\"journal\":{\"name\":\"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)\",\"volume\":\"41 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-11-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APCCAS55924.2022.10090394\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS55924.2022.10090394","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Low-Noise Neural Signal Amplifier Achieving 1.6 NEF and 2.56 PEF for Brain-Machine Interface
This paper presents a low-power and low-noise front-end amplifier (FEA) dedicated to recording and preprocessing biomedical signals for brain-machine interface. The FEA employs a current-reused architecture which adopts an inverter-based differential input stage to achieve considerable $g_{m}/I$ efficiency and low noise. With a carefully designed common-mode feedback circuit, the output common-mode voltage of the fully-differential FEA is stabilized within an acceptable margin of error about 1 mV. All transistors in FEA operate in the sub-threshold region, realizing low power consumption. This current-reused FEA implemented in a CMOS 0.18- $\mu \mathbf{m}$ technology provides a noise efficiency factor (NEF) and power efficiency factor (PEF) of 1.6 and 2.56, respectively, corresponding to an input-referred noise of 2.37 $\mu \boldsymbol{V}_{rms}$. This FEA consumes only 2 $\mu \mathbf{A}$ current from 1 V supply and the active area is $0.2 \ \mathbf{mm} \times 0.2$ mm.