界面态的产生导致短沟道mosfet的导通电压下降

I. Eisele, P. Vitanov, F. Fischer, U. Schwabe
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引用次数: 0

摘要

对于规模化Mos器件,导通电压的长期可靠性非常重要。在应力老化2000 h (T=150℃)下,测量了导通电压的长期稳定性。E = 2.5×106 v /厘米)。产生的界面陷阱没有必要的平带移位观察。尽管如此,当有效通道长度L<2.0¿m时,出现正的导通电压移位。应力测量已在多晶体管结构上进行,该结构允许在同一测试结构上测量界面陷阱、阈值电压和特征尺寸。从有效通道长度的角度讨论了导通电压位移与界面阱密度之间的关系。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Turn-On Voltage Degradation of Short Channel MOSFETs Due to Generation of Interface States
For scaled Mos devices long term reliability of the turn-on voltage is important. Longterm stability of the turn-on voltage has been measured under stress aging for 2000 h (T=150°C. E=2.5×106V/cm). Generation of interface traps without essential flatband shift is observed. Despite that, positive turn-on voltage shift appears for effective channel lengths L<2.0¿m. The stress measurements have been performed on multitransistor structures which permit to measure interface traps, threshold voltage, and feature sizes on the same test structure. The relationship between the turn-on voltage shift and the interface trap density is discussed with respect to the effective channel length.
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