TLP胁迫下ggest的上升时间效应

2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400) Pub Date : 2000-05-14 DOI:10.1109/ICMEL.2000.840588

G. Boselli, A. Mouthaan, F. Kuper

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引用次数: 8

摘要

本文利用混合模模拟器在亚纳秒范围内详细分析了在TLP应力作用下，接地栅极nMOS晶体管(ggnMOS)寄生双极晶体管导通的主要机制。我们发现，在静态条件下测量的ggnMOS击穿电压会低估TLP应力在保护结构上获得的最大电压，这取决于所施加脉冲的上升时间。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Rise-time effects in ggnMOSt under TLP stress

In this paper the main mechanisms that lead the turn on of the parasitic bipolar transistor of a grounded gate nMOS transistor (ggnMOS) under TLP stress have been analyzed in detail in the sub-nanoseconds range by means of a mixed-mode simulator. We showed that the breakdown voltage of the ggnMOS measured in static conditions would underestimate the maximum voltage across the protection structure obtained by TLP stress, depending on the rise-time of the applied pulse.

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2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400)

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