R. Thirunarayanan, D. Ruffieux, N. Scolari, C. Enz
{"title":"51.4 Mb/s FSK发射机,采用相位域数字合成器,1.5µs启动,节能占空比","authors":"R. Thirunarayanan, D. Ruffieux, N. Scolari, C. Enz","doi":"10.1109/ESSCIRC.2016.7598259","DOIUrl":null,"url":null,"abstract":"This paper presents a low start-up latency Transmitter (TX) that can achieve FSK data rates of upto 51.4 Mb/s for deployment in duty cycled microsensor nodes. Utilizing a Phase Domain Digital Synthesizer with an FBAR frequency reference, this TX has a start-up latency of just 1.5 μs. It has been integrated in a 65nm technology and outputs upto 3 dBm power. It achieves a phase noise of -110 dBc/Hz at 1 MHz offset and has a frequency coverage of 2.17 - 2.47 GHz. The power consumption of this TX (including the Digital Baseband) varies from 15 mW at 1.2 Mb/s to 21.4 mW at 51.4 Mb/s. At peak data rate, this leads to an Duty-Cycling-Energy/bit (which takes into account the start-up energy) of 500 pJ/b for transmitting packets of length 32 bytes. Moreover, the TX incorporates a Hybrid Requantizer circuit which helps to trade off in-band noise with the spurs due to the non-linearity induced ΣΔ noise folding.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"74 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 51.4 Mb/s FSK transmitter employing a Phase Domain Digital Synthesizer with 1.5 µs start-up for energy efficient duty cycling\",\"authors\":\"R. Thirunarayanan, D. Ruffieux, N. Scolari, C. Enz\",\"doi\":\"10.1109/ESSCIRC.2016.7598259\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a low start-up latency Transmitter (TX) that can achieve FSK data rates of upto 51.4 Mb/s for deployment in duty cycled microsensor nodes. Utilizing a Phase Domain Digital Synthesizer with an FBAR frequency reference, this TX has a start-up latency of just 1.5 μs. It has been integrated in a 65nm technology and outputs upto 3 dBm power. It achieves a phase noise of -110 dBc/Hz at 1 MHz offset and has a frequency coverage of 2.17 - 2.47 GHz. The power consumption of this TX (including the Digital Baseband) varies from 15 mW at 1.2 Mb/s to 21.4 mW at 51.4 Mb/s. At peak data rate, this leads to an Duty-Cycling-Energy/bit (which takes into account the start-up energy) of 500 pJ/b for transmitting packets of length 32 bytes. Moreover, the TX incorporates a Hybrid Requantizer circuit which helps to trade off in-band noise with the spurs due to the non-linearity induced ΣΔ noise folding.\",\"PeriodicalId\":246471,\"journal\":{\"name\":\"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference\",\"volume\":\"74 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2016.7598259\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2016.7598259","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 51.4 Mb/s FSK transmitter employing a Phase Domain Digital Synthesizer with 1.5 µs start-up for energy efficient duty cycling
This paper presents a low start-up latency Transmitter (TX) that can achieve FSK data rates of upto 51.4 Mb/s for deployment in duty cycled microsensor nodes. Utilizing a Phase Domain Digital Synthesizer with an FBAR frequency reference, this TX has a start-up latency of just 1.5 μs. It has been integrated in a 65nm technology and outputs upto 3 dBm power. It achieves a phase noise of -110 dBc/Hz at 1 MHz offset and has a frequency coverage of 2.17 - 2.47 GHz. The power consumption of this TX (including the Digital Baseband) varies from 15 mW at 1.2 Mb/s to 21.4 mW at 51.4 Mb/s. At peak data rate, this leads to an Duty-Cycling-Energy/bit (which takes into account the start-up energy) of 500 pJ/b for transmitting packets of length 32 bytes. Moreover, the TX incorporates a Hybrid Requantizer circuit which helps to trade off in-band noise with the spurs due to the non-linearity induced ΣΔ noise folding.