基于整数硬件算法的单通量量子电子学计算能量效率分析

2013 IEEE 14th International Superconductive Electronics Conference (ISEC) Pub Date : 2013-07-07 DOI:10.1109/ISEC.2013.6604280

Q. Xu, Y. Shimamura, Y. Yamanashi, N. Yoshikawa, T. Ortlepp

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引用次数: 2

摘要

我们设计并实现了一种基于单通量量子(SFQ)的硬件算法，称为3n+1猜想。该电路由16位整数寄存器、高频时钟发生器和中央处理器组成。本设计基于AIST 10 kA/cm2先进Nb工艺，时钟频率最高可达90 GHz，总功耗约为0.85 mW。通过使用lr偏置方法，进一步降低了功耗。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Analysis of computational energy efficiency in single-flux-quantum electronics by implementing an integer-based hardware-algorithm

We designed and implemented a single-flux-quantum (SFQ) based hardware-algorithm known as the 3n+1 conjecture. The circuit consists of a 16-bit integer register, a high-frequency clock generator and a central processor. This design can perform with a maximum clock frequency of 90 GHz with a total power consumption of about 0.85 mW based on the AIST 10 kA/cm2 advanced Nb process. The power consumption was further reduced by using an LR-biasing approach.

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2013 IEEE 14th International Superconductive Electronics Conference (ISEC)

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