读使能(RE)信号占空比失真(DCD)对NAND闪存SI仿真的影响

2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI:10.1109/EPEPS.2017.8329702

Sayed Mobin, Balaji Raghunathan, Arkady Katz

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引用次数: 3

摘要

在NAND到闪存管理控制器(FMC) SI仿真中，必须集成读使能(RE)信号占空比失真(DCD)的影响，以准确预测多芯片高性能系统的系统级性能。假设NAND驱动器输入端的占空比为50%是过于乐观的。FMC和NAND都在NAND读周期中造成部分占空比失真。本文确定了传统SI模拟中的差距，并描述了如何通过包括现实的RE DCD来减少模拟流程中的这种差距。为了进行相关，测量了模具液位信号，并观察到测量结果与仿真结果之间存在良好的相关性，表明了所提出的更改的重要性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Impact of read enable (RE) signal duty cycle distortion (DCD) in NAND flash SI simulation

Impact of Read Enable (RE) signal's Duty Cycle Distortion (DCD) must be integrated in NAND to Flash Management Controller (FMC) SI simulation to predict system level performance accurately in multi-die, high performance systems. Assuming 50% duty cycle signal at the input to NAND driver is too optimistic. Both FMC and NAND contribute a portion of duty cycle distortion in the NAND read cycle. This paper identifies the gap in conventional SI simulation and describes how to reduce this gap in the simulation flow by including realistic RE DCD. Die level signals were measured for correlation purpose, and good correlation was observed between the measurements and simulations, demonstrating the importance of proposed changes.

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来源期刊

2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)

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