Yihong Li, Sikai Chen, Yunqi Yang, Qianli Ma, Ming Zhong, Ziyi Lin, Leliang Li, Guike Li, Zhao Zhang, Liyuan Liu, Jian Liu, N. Wu, Yong Chen, Qi Peng, Nan Qi
{"title":"基于45nm SOI CMOS的50gb /s低延迟多芯片模块光I/O NRZ接收器","authors":"Yihong Li, Sikai Chen, Yunqi Yang, Qianli Ma, Ming Zhong, Ziyi Lin, Leliang Li, Guike Li, Zhao Zhang, Liyuan Liu, Jian Liu, N. Wu, Yong Chen, Qi Peng, Nan Qi","doi":"10.1109/APCCAS55924.2022.10090261","DOIUrl":null,"url":null,"abstract":"This paper presents a 50-Gb/s optical receiver chipset in 45-nm silicon-on-insulator (SOI) CMOS. It comprises a trans-impedance amplifier (TIA) cascaded by a clock and data recovery circuits (CDR). Inverter-based topology with hybrid-peaking inductors is designed to improve the TIA bandwidth (BW). Phase-interpolator-based digital CDR with a baud-rate sampling phase detector is developed for multi-channel integration and low power consumption. Measurements show that the TIA achieves a 53-dBΩ gain and a 27-GHz BW of S21. The receiver prototype outputs a 3.125-GHz recovered clock with −125.84-dBc/Hz@10MHz phase noise and 6.25-Gb/s deserialized data with a 3.5-ps RMS jitter.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 50-Gb/s NRZ Receiver Targeting Low-Latency Multi-Chip Module Optical I/O in 45-nm SOI CMOS\",\"authors\":\"Yihong Li, Sikai Chen, Yunqi Yang, Qianli Ma, Ming Zhong, Ziyi Lin, Leliang Li, Guike Li, Zhao Zhang, Liyuan Liu, Jian Liu, N. Wu, Yong Chen, Qi Peng, Nan Qi\",\"doi\":\"10.1109/APCCAS55924.2022.10090261\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a 50-Gb/s optical receiver chipset in 45-nm silicon-on-insulator (SOI) CMOS. It comprises a trans-impedance amplifier (TIA) cascaded by a clock and data recovery circuits (CDR). Inverter-based topology with hybrid-peaking inductors is designed to improve the TIA bandwidth (BW). Phase-interpolator-based digital CDR with a baud-rate sampling phase detector is developed for multi-channel integration and low power consumption. Measurements show that the TIA achieves a 53-dBΩ gain and a 27-GHz BW of S21. The receiver prototype outputs a 3.125-GHz recovered clock with −125.84-dBc/Hz@10MHz phase noise and 6.25-Gb/s deserialized data with a 3.5-ps RMS jitter.\",\"PeriodicalId\":243739,\"journal\":{\"name\":\"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-11-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APCCAS55924.2022.10090261\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS55924.2022.10090261","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 50-Gb/s NRZ Receiver Targeting Low-Latency Multi-Chip Module Optical I/O in 45-nm SOI CMOS
This paper presents a 50-Gb/s optical receiver chipset in 45-nm silicon-on-insulator (SOI) CMOS. It comprises a trans-impedance amplifier (TIA) cascaded by a clock and data recovery circuits (CDR). Inverter-based topology with hybrid-peaking inductors is designed to improve the TIA bandwidth (BW). Phase-interpolator-based digital CDR with a baud-rate sampling phase detector is developed for multi-channel integration and low power consumption. Measurements show that the TIA achieves a 53-dBΩ gain and a 27-GHz BW of S21. The receiver prototype outputs a 3.125-GHz recovered clock with −125.84-dBc/Hz@10MHz phase noise and 6.25-Gb/s deserialized data with a 3.5-ps RMS jitter.
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