Computing Gate Asymmetric Effect on Drain Current of DG-MOSFET following Ortiz-Conde Model

Asymmetric gate effect on ID-VSD characteristic of p-type Si1-xGex double-gate MOSFET is analytically investigated following Ortiz-Conde model. Position of maximum potential w.r.t centre point is computed, and corresponding centre potential is measured; which is included for drain current calculation. Different barrier height at the top and bottom gates are considered which effectively provides the shift of surface potential, and result is compared with that obtained for conventional symmetric device; as obtained from Ortiz-Conde model. Channel length, external biases and dielectric properties are also varied to observe the shift of saturation current, where Fowler-Nordheim tunneling probability is invoked owing to thinner dielectric layer. Results are key for amplifier design using DGMOSFET for optimum gain.