高速集成电路设计中选择片上旁路电容的电源寄生特性建模

Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004. Pub Date : 2004-09-08 DOI:10.1109/SMIC.2004.1398196

Qiurong He, M. Feng

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引用次数: 0

摘要

我们建立了一个电源寄生模型，以便在高速集成电路设计中正确选择片上旁路电容值。该模型可以使芯片面积最小化，同时保持电路性能。描述了开发该模型的过程，该模型适用于所有设备技术。设计并制作了一种带宽为10ghz的InGaP/GaAs HBT跨阻放大器。该模型的仿真结果与实测结果吻合较好。

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Modeling of power supply parasitics for selecting on-wafer bypass capacitance in high-speed IC designs

We have developed a model for power supply parasitics to select properly the on-wafer bypass capacitor values in high-speed IC designs. The model can allows the chip area to be minimized while maintaining circuit performance. The procedures to develop this model are described and are suitable for all device technologies. An InGaP/GaAs HBT transimpedance amplifier with 10-GHz bandwidth was designed and fabricated. The simulation with the model matches the measured results very well.

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来源期刊

Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.

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