SOC硬件无故障仿真

2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI:10.1109/MIXDES.2007.4286197

V. Hahanov, M. Kaminska, W. Ghribi, A. Hahanova

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引用次数: 0

摘要

本文给出了数字器件的结构功能多值硬件模型;针对时序结构的多输入模式联合仿真和多增益性能瞬态分析，提出了数字器件的双电路结构功能多值硬件模型;提出了用于数字系统片上分析和硬件验证的hdl码传输到数据结构的自动模型。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Hardware Fault Free Simulation for SOC

In the paper structure functional multi-valued hardware model of digital device is offered; two-circuits structure functional multi-valued hardware model of digital device for multiple input patterns co-simulation and multiple increasing of performance transient analysis in sequential structures is proposed; automatic model of HDL-code transmission process to data structure for digital system on chip analysis and verification with hardware is proposed.

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2007 14th International Conference on Mixed Design of Integrated Circuits and Systems

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