Improved linearity standard cell based flash ADC with DBNS encoding scheme

In this paper three different designs are discussed in term of their linearity. Proposed ADC consists of a linearity improved comparator scheme consist of CMOS standard cells (NAND, NOR) in place of Inverter based comparators which eliminate need of feature size variation. Instead of using traditional encoding strategy; Double Base Number System based encoder assembled with ADC to improve speed. This assembly can process arithmetic operations fast due to its multidimensional logarithmic number feature.