Enhanced Drain Current in Transient Mode due to Long Ionization Time of Shallow Impurities at 4 K in 65-nm bulk Cryo CMOS Transistors

Despite the importance of cryo CMOS technologies in quantum computing systems, the transient behaviors of cryo MOS transistors have been less studied. In this work, in advanced CMOS transistors we observed sub-us transient drain current $(I_{\mathrm{d}}^{\text{Trans}})$ that was much greater than the static drain current $(I_{\mathrm{d}}^{\text{Static}})$ at 4 K (Fig. 6); the transient-to-static ratio $r\equiv I_{\mathrm{d}}^{\text{Trans}}/I_{\mathrm{d}}^{\text{Static}}$ reached as large as 2.7 (Fig. 9), whereas $r$ stays at one in the same device at 20 K. The observed transient characteristics are not due to the self-heating effects, but due to the long emission time of holes from acceptors at 4 K. After applying biases, more electrons flow into the channel than those in static conditions to mitigate the frozen acceptors. $I_{\mathrm{d}}^{\text{Trans}}$. goes down to $I_{\mathrm{d}}^{\text{Static}}$ because of gradual ionization of acceptors. We consider that the observed transient behavior needs to be considered in cryo MOSFET model to accurately design cryo LSI circuits.