集成电路封装过程中残余应力演化的数值预测

A. R. Rezaie Adliv, K. Jansen, L. Ernst
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引用次数: 0

摘要

本文建立了一个计算集成电路封装过程中残余应力的数值本构模型。残余应力是成型过程的结果,可分为固化和热致零件。热致应力的检测在文献中一直被忽视,而热致应力的检测一直受到人们的特别关注。在本研究中,两种封装导致的应力分别进行了独立研究,并基于成型各阶段的应用边界条件和已建立的工艺相关力学模型开发了一种数值方法。二维数值模型是在一个商用软件包中实现的。通过在传递成型过程中实现压阻式应力测量芯片,验证了数值预测的应力结果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Numerical prediction of residual stresses evolving during packaging of ICs
This paper comprises a numerical constitutive model for evaluating residual stresses generated during encapsulation of integrated circuits. Residual stress is a consequence of molding process which can be divided in cure and thermal induced parts. Cure originated stress had been mostly neglected in literature and a special attention had always been given to detection of thermal induced stresses. In this study, both encapsulation resulted stresses are studied independently and a numerical methodology has been developed based on the applied boundary conditions during each stage of molding and the established process dependent mechanical models. A two dimensional numerical model is implemented in a commercially available software package. The numerically predicted stress results are experimentally validated by implementing a piezoresistive stress measuring chip in a transfer molding process.
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