SoC中功率域问题的评估方法

J. Cetin, A. Balasinski
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引用次数: 0

摘要

电源电压的噪声可以通过调制与其驱动电流相关的各个模块的信号频率来干扰SoC的工作。这种干扰通常是由于SoC的复杂功能加上它们的低引脚数和电流路由不支持芯片不同部分的功率需求。由于技术缩小,引脚数最小化,以帮助利用芯片面积减少的优势,需要更少的功率域,从而增加每个域的电流。由于功能的增加,再加上布线到模具上目标位置的电阻和电感更大,导致直流(IR)和瞬态(L di/dt)电压下降,其严重程度随着每一代产品的产生而增加。同时,由于电源电流和电压的分布式特性,配电的“热点”难以识别。在这项工作中,提出了一种评估SoC中功率域问题的新方法,该方法基于对总模具功率分布的多层次分析,以帮助确定应该使用哪些设计工具以及在何种复杂级别上使用。从最初的标准(即硅验证)开始,建议在硅上验证的域不需要功率域分析。然后表明,如果可以证明足够的静态和动态功率安全裕度,则初级水平的分析是足够的。在这种分析中,可能需要执行相对简单的块级评估,以确保产品在标准封装中的功能,具体取决于线路电感和工作频率。对于高芯片电流水平,需要使用先进的设计工具来解决每个电流节点和电压环内的问题,并且初步分析可以帮助定义关键域。在整个设计评审过程中应如何考虑供电系统的噪声
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Method to Evaluate Power Domain Problems in SoC
Noise of the power supply voltage can disturb SoC operation by modulating signal frequency of its individual blocks related to their drive current. This disturbance typically results from the complex functions of the SoC combined with their low pin count and current routing not supporting the power demand in the different sections of the die. The pin count, minimized to help take advantage of die area reduction due to technology shrinks calls for fewer power domains resulting in an increase of the current per domain. This, combined with the larger resistance and inductance of the wiring to the target location on the die, due to the increased functionality, gives rise to the DC (IR) and transient (L di/dt) voltage droop, the severity of which increases with every product generation. At the same time, the "hot spots" of power distribution are difficult to identify due to the distributed nature of the power supply current and voltage. In this work, a novel approach to evaluate power domain problems in SoC was proposed, based on a multi-level analysis of the distribution of total die power to help determine what design tools should be engaged and at which complexity level. Starting from the initial criterion i.e., silicon verification, it was recommended that power domain analysis is not required for the domains proven on silicon. It was then shown that the analysis at a rudimentary level is sufficient if adequate static and dynamic power safety margins can be proven. In such analysis, one may need to perform a relatively simple block level assessment to ensure product functionality in a standard package, depending on the line inductance and operating frequency. For the high die current levels, one would be required to use advanced design tools to resolve problems within every current node and voltage loop, and the preliminary analysis can help define the critical domains. How the noise of the power supply system should be considered throughout the design review process was shown
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