1.2V, 140GHz接收器,65nm CMOS片上天线

S. Nicolson, A. Tomkins, K. W. Tang, A. Cathelin, D. Belot, S. Voinigescu
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引用次数: 85

摘要

本文设计了一种1.2 V、100 mW、140 GHz的片上天线接收器,采用65 nm通用CMOS工艺和数字后端。该接收机在100-140 GHz范围内的转换损耗为15-19 dB,本端电压为102 GHz,其芯片面积仅为580 μ m × 700 μ m(含焊盘)。LNA在140 GHz时可获得8db增益,带宽为10 GHz,饱和输出功率至少为-1.8 dBm,在125℃时可保持3db增益。片上天线满足65 nm CMOS的所有密度填充要求,增益为-25 dB,占用180 μ m × 100 μ m的芯片面积。此外,还讨论了最大化CMOS器件毫米波性能的设计技术。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 1.2V, 140GHz receiver with on-die antenna in 65nm CMOS
This paper presents a 1.2 V, 100 mW, 140 GHz receiver with on-die antenna in a 65 nm General Purpose (GP) CMOS process with digital back-end. The receiver has a conversion loss of 15-19 dB in the 100-140 GHz range with 102 GHz LO, and occupies a die area of only 580 mum times 700 mum including pads. The LNA achieves 8 dB gain at 140 GHz, 10 GHz bandwidth, at least -1.8 dBm of saturated output power, and maintains 3 dB gain at 125 degC. The on-chip antenna, which meets all density fill requirements of 65 nm CMOS, has -25 dB gain, and occupies 180 mum times 100 mum of die area. Additionally, design techniques which maximize the millimeter-wave performance of CMOS devices are discussed.
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