Timing yield-aware color reassignment and detailed placement perturbation for double patterning lithography

Double patterning lithography (DPL) is a likely resolution enhancement technique for IC production in 32 nm and below technology nodes. However, DPL gives rise to two independent, un-correlated distributions of linewidth on a chip, resulting in a 'bimodal' linewidth distribution and an increase in performance variation. suggested that new physical design mechanisms could reduce harmful covariance terms that contribute to this performance variation. In this paper, we propose new bimodal-aware timing analysis and optimization methods to improve timing yield of standard-cell based designs that are manufactured using DPL. Our first contribution is a DPL-aware approach to timing modeling, based on detailed analysis of cell layouts. Our second contribution is an ILP-based maximization of 'alternate' mask coloring of instances in timing-critical paths, to minimize harmful covariance and performance variation. Third, we propose a dynamic programming-based detailed placement algorithm that solves mask coloring conflicts and can be used to ensure ¿double patterning correctness¿ after placement or even after detailed routing, while minimizing the displacement of timing-critical cells with manageable ECO impact. With a 45 nm library and open-source design testcases, our timing-aware recoloring and placement optimizations together achieve up to 232 ps (resp. 36.22 ns) reduction in worst (resp. total) negative slack, and 78% (resp. 65%) reduction in worst (resp. total) negative slack variation.