{"title":"具有速度超调特性的SOI外延沟道Si-MOSFET","authors":"L. Beer, W. Appel, V. Dudek, B. Hofflinger","doi":"10.1109/CORNEL.1995.482538","DOIUrl":null,"url":null,"abstract":"A novel device fabrication process using selective silicon epitaxy with lateral overgrowth and in-situ channel region generation by dopant switching during the growth process is presented. Based on this procedure SOI MOSFETs with channel lengths down to 100 nm were produced completely independent of lithographical resolution restrictions. Together with a 6 nm oxinitride gate dielectric, an intrinsic transconductance of up to 700 mS/mm was obtained at room temperature.","PeriodicalId":268401,"journal":{"name":"Proceedings IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A SOI epitaxial-channel Si-MOSFET with velocity overshoot\",\"authors\":\"L. Beer, W. Appel, V. Dudek, B. Hofflinger\",\"doi\":\"10.1109/CORNEL.1995.482538\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel device fabrication process using selective silicon epitaxy with lateral overgrowth and in-situ channel region generation by dopant switching during the growth process is presented. Based on this procedure SOI MOSFETs with channel lengths down to 100 nm were produced completely independent of lithographical resolution restrictions. Together with a 6 nm oxinitride gate dielectric, an intrinsic transconductance of up to 700 mS/mm was obtained at room temperature.\",\"PeriodicalId\":268401,\"journal\":{\"name\":\"Proceedings IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CORNEL.1995.482538\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CORNEL.1995.482538","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A SOI epitaxial-channel Si-MOSFET with velocity overshoot
A novel device fabrication process using selective silicon epitaxy with lateral overgrowth and in-situ channel region generation by dopant switching during the growth process is presented. Based on this procedure SOI MOSFETs with channel lengths down to 100 nm were produced completely independent of lithographical resolution restrictions. Together with a 6 nm oxinitride gate dielectric, an intrinsic transconductance of up to 700 mS/mm was obtained at room temperature.