用于脉冲压缩的低损耗低成本全硅CMOS nltl

M. Li, R. Amaya, J. Duchamp, P. Ferrari, R. Harrison, N. G. Tarr
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引用次数: 4

摘要

本文讨论了采用标准0.18 μ m CMOS工艺的全硅脉冲压缩非线性传输线(NLTLs)的设计。研究了两种不同类型的基于NMOS晶体管的变容管。一种类型用于单刃,另一种用于双刃脉冲锐化器NLTL。为了减少导电硅衬底造成的损耗,采用了慢波传输线技术。在40 GHz时,测量到的S21损耗仅为0.25 dB/mm。制作了NMOS变容管和慢波共面波导(CPW)两种用于NLTL设计的传输线元件,并进行了片上测量。基于测量的瞬态仿真表明,单刃脉冲锐化可以减少75%的前缘上升时间,双刃脉冲锐化可以减少60%的前缘上升时间。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Low-Loss Low-Cost All-Silicon CMOS NLTLs for Pulse Compression
This paper discusses the design of all-silicon pulse-compression nonlinear transmission lines (NLTLs), using a standard 0.18-mum CMOS process. Two different types of varactors based on NMOS transistors are investigated. One type is used in a single-edge, the other in a double-edge pulse-sharpener NLTL. To reduce the loss caused by conductive silicon substrate, a slow-wave transmission line technique is used. A measured S21 loss of only 0.25 dB/mm at 40 GHz is achieved. Both NMOS varactor and slow-wave coplanar-waveguide (CPW) transmission-line components for use in NLTL designs were fabricated and on-chip measurements were made. Transient simulations based on the measurements show a leading edge rise time reduction of 75% for single-edge, and 60% for double-edge pulse sharpening.
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