1.7-W 50gbit /s InP HEMT 4:1多路复用IC，采用多相时钟架构

24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu Pub Date : 2002-12-10 DOI:10.1109/GAAS.2002.1049051

K. Sano, Koichi Murata, S. Sugitani, H. Sugahara, T. Enoki

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引用次数: 7

摘要

报道了一种具有多相时钟结构的4:1多路复用集成电路的低功耗和高速工作。该架构具有一个产生四相时钟的切换型触发器(TFF)和一个串行门控4:1选择器(SEL)。使用InP hemt制作的集成电路工作在50 Gbit/s无误差，功耗为1.71 w，输出幅度为1 vpp。功耗小于传统树型InP HEMT 4:1多路复用器IC的1/3，并且在不降低操作速度和输出幅度的情况下实现。

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1.7-W 50-Gbit/s InP HEMT 4:1 multiplexer IC with a multi-phase clock architecture

Low-power and high-speed operation of a 4:1 multiplexer IC with a multi-phase clock architecture is reported. The architecture features a toggle-type flip-flop (TFF) that generates a four-phase clock, and a series-gated 4:1 selector (SEL). The fabricated IC using InP HEMTs operates at 50 Gbit/s error-free with 1.71-W power consumption and 1-Vpp output amplitude. The power consumption is less than 1/3 that of a conventional tree-type InP HEMT 4:1 multiplexer IC and is achieved without any reduction of operation speed and output amplitude.

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24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu

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