时序电路多卡断故障的伪穷举测试

A. Matrosova, E. Mitrofanov
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引用次数: 3

摘要

顺序电路设计是基于对组合部件的行为进行混合描述。该行为由robdd和单调乘积组成。该设计方法提供了顺序电路组合部分的完全延迟可测试性。结果表明,该方法还能提供组合件的多卡滞故障可测性。提出了由两部分组成的拟穷举检验方法。一部分用于测试由基本电路(逆变与异或电路)覆盖适当的robdd节点获得的子电路。它允许在远离组合部分输入的基本电路栅极均匀地检测多个卡在故障。第二测试部分检测组合部分其余部分栅极处的所有多个卡死故障。假定一个组合部件的这两个部件中只有一个可能有故障。给出了测试时间的估计。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Pseudo-exhaustive testing of sequential circuits for multiple stuck-at faults
A Sequential circuit design is based on using mixed description of a behavior of a combinational part. The behavior is represented with a composition of ROBDDs and monotonous products. The design method provides fully delay testability of a combinational part of a sequential circuit. In this paper it is shown that the method also provides multiple stuck-at faults testability of a combinational part. The pseudo-exhaustive test consisting of two parts is developed. One part is used to test sub-circuits obtained by covering nodes of the proper ROBDDs by elementary circuits (Invert-AND-XOR circuits). It allows detecting multiple stuck-at faults at gate poles of elementary circuits evenly remote from the combinational part inputs. The second test part detects all multiple stuck-at faults at gate poles of the rest component of the combinational part. It is supposed that only one of these two components of a combinational part may be faulty. An estimation of the length of such test is given.
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