背面嵌硅电感，采用磁层进行屏蔽和电感增强

2013 IEEE International Conference of Electron Devices and Solid-state Circuits Pub Date : 2013-06-03 DOI:10.1109/EDSSC.2013.6628231

Rongxiang Wu, Wei Li, Yong Ren, Heping Luo, Guojun Zhang

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引用次数: 0

摘要

本文提出并研究了一种基于磁层的背面嵌硅电感(BSEI)，用于磁通屏蔽和电感增强。通过磁层，BSEI芯片下的磁通量降低了2到3倍，因此在Cu模垫的存在下，BSEI性能的显著下降被有效抑制。磁层的加入也使BSEI的电感提高了30%。这使得BSEI在芯片供电应用中更有前景。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Backside silicon-embedded inductor using magnetic layer for shielding and inductance enhancement

In this paper, a backside silicon-embedded inductor (BSEI) using a magnetic layer is proposed and studied for magnetic flux shielding and inductance enhancement. With the magnetic layer, the magnetic flux that goes under the BSEI chip is reduced by 2 to 3 times, and consequently the significant BSEI performance degradation in presence of a Cu die pad is effectively suppressed. The inductance of the BSEI is also enhanced by 30% with the magnetic layer. This makes the BSEI more promising for power supply-on-chip applications.

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2013 IEEE International Conference of Electron Devices and Solid-state Circuits

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