DDR2存储器供电网络的设计、分析与优化

2007 IEEE Electrical Performance of Electronic Packaging Pub Date : 2007-11-21 DOI:10.1109/EPEP.2007.4387131

Junho Lee, Hyunseok Kim, Kimyung Kyung, Minyoung You, Hyungdong Lee, Kunwoo Park, Byong-Tae Chung

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引用次数: 3

摘要

本文介绍了DDR2存储芯片供电网络的设计过程和分析方法。通过调整电源/地片垫的位置和片上去耦电容的W/L大小，优化存储芯片的供电网络。结果表明，合理设计的电源/地芯片衬垫和去耦电容器可大大降低功率噪声，从而减少片上去耦电容器的面积，从而降低芯片成本。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design, Analysis, and Optimization of DDR2 Memory Power Delivery Network

In this paper, design procedure and analysis method of power delivery network of DDR2 memory chip are introduced. The power delivery network of memory chip is optimized by tuning the location of power/ground chip pad and on-chip decoupling capacitor's W/L size. The results show that the properly designed power/ground chip pads and decoupling capacitors greatly reduce power noise, resulting in the reduction of chip cost by using less area for on-chip decoupling capacitor.

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来源期刊

2007 IEEE Electrical Performance of Electronic Packaging

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