从SysML到Petri网的嵌入式系统形式化验证转换

2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI:10.23919/MIXDES.2018.8436870

W. Szmuc, T. Szmuc

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引用次数: 4

摘要

考虑了使用SysML描述的嵌入式系统的验证。其主要思想是将SysML工件转换为彩色Petri网模型。本文的重点是将主要建筑单元，即所谓的街区映射到相应的网中。这些网可以直接验证，也可以使用时态逻辑证明器进行验证。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Towards Embedded Systems Formal Verification Translation from SysML into Petri Nets

A verification of embedded systems described using SysML is considered. The main idea consists in translation of SysML artifacts into Colored Petri Net models. The paper focuses on mapping of main building units, the so-called blocks into the corresponding nets. The nets may be verified directly or using Temporal Logic provers.

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2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES)

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