Identifying DC bias conditions for maximum DC current in digitally-assisted analog design

We propose a novel methodology for maximizing DC current in digitally-assisted analog circuit. The proposed methodology identifies a set of analog bias voltages and digital mode selection signals that maximizes the DC current through either a particular wire segment or the power/ground bus. This technique enables sensitization of EM related faults. First, a channel-connected graph is built from a mixed signal transistor circuit, then the current activation condition is formulated as satisfiability constraints annotated in the channel-connected graph. This results in a weighted constraint satisfaction(WCS) formulation. To the best of author's knowledge, this problem has not been previously studied.