双端口SRAM读-扰-写机制及测试设计

2017 Joint International Symposium on e-Manufacturing and Design Collaboration (eMDC) & Semiconductor Manufacturing (ISSM) Pub Date : 2017-09-01 DOI:10.23919/ISSM.2017.8089088

R. Lo, S. Lu, Jordan Hsu, Quincy Li

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引用次数: 2

摘要

双端口(DP)需要异步时钟倾斜测试，以在从两个端口同时访问行期间屏蔽读-扰-写。我们将从仿真和Si两方面解释读-扰动-写失效机制。采用BL箝位设计和更长的写入字-线-脉冲方案提高了DP Vmin，并提出了二维自适应shmoo，减少了测试时间。

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Dual port SRAM read-disturb-write mechanism and design for test

Dual Port (DP) needs asynchronous clock skew test to screen out read-disturb-write during simultaneous row access from both ports. We will explain read-disturb-write failure mechanism from simulation and Si. The BL clamped design and longer write word-line-pulse scheme can improve DP Vmin. 2D adaptive shmoo is also proposed to reduce test time.

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2017 Joint International Symposium on e-Manufacturing and Design Collaboration (eMDC) & Semiconductor Manufacturing (ISSM)

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