Formalizing Signature Analysis for Control Flow Checking of Pipelined RISC Microprocessors

This paper focuses on the adaptation of a concurrent control-flow checking technique to pipelined RISC microprocessors. This technique, called embedded signature monitoring (ESM), verifies the validity of the instructions executed by the processor. Numerous ESM schemes have been studied with non pipelined processors but up-to-date machines pose new problems. The instruction pipeline of these processors makes difficult to know which instructions are actually executed among the fetched ones: the pipeline may be flushed when a jlowcontrol instruction is executed or when an exception is taken. A behavioural model is presented for the pipeline of most recent processors. It is used to propose a new simple ESM scheme compatible with these processors. This scheme is experienced on the Motorola MC88100 RISC processor. The design of a signature monitor dedicated to this processor is presented and hardware costs are discussed.