DFM / DFT /硅调试/诊断

S. Venkataraman, Nagesh Tamarapalli
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引用次数: 0

摘要

半导体成品率历来受到随机粒子缺陷问题的限制。然而,当特征尺寸减小到0.13微米及以下时,系统机制限制的产量损失开始成为产量损失的重要组成部分。此外,越来越明显的是,提高收益率将需要更长的时间,最终收益率将达不到历史标准。没有达到以前达到的产量水平的一个关键因素是设计和制造之间的相互作用。新工艺的产量损失包括功能缺陷、参数缺陷和测试问题。每一种产量损失的来源都需要设计者和工具开发者进行分析和理解。此外,必须设计新的技术和方法,以尽量减少这些产量损失机制的影响。在介绍了第一部分中涉及的问题之后,第二部分将介绍用于分析设计内容的面向制造的设计(DFM)技术,标记可能限制产量的设计区域,并进行更改以提高产量。然而,一旦做出改变,就有必要量化它们的影响,以便将有关不同特征对产量贡献的知识反馈给设计和DFM工具。在自动测试模式生成(ATPG)期间,通过制作测试模式来暴露容易出现缺陷的特征,以及通过诊断分析硅故障来确定实际导致产量损失的特征及其相对影响,测试提供了一个关闭循环的机会。第三部分涵盖了设计技术(DFX),以提高可测试性、可调试性和可诊断性,以及DFM和缺陷感知测试生成,以满足产品质量和暴露测试中的良率问题。第四部分涵盖了调试诊断的基本概念和理论方面,包括算法IC诊断、扫描链诊断、基于关键路径的技术和延迟缺陷诊断。硅调试的基本概念和技术的应用将在第五节中介绍。第六节涵盖了统计诊断技术的应用,以确定实际导致产量损失及其相对影响的特征。最后,在第七部分,未来的趋势,挑战和方向是涵盖。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
DFM / DFT / SiliconDebug / Diagnosis
Semiconductor yield has traditionally been limited by random particle-defect based issues. However, as the feature sizes reduced to 0.13 micron and below, systematic mechanism-limited yield loss began to appear as a substantial component in yield loss. In addition, it is becoming clear that ramping yield would take longer and final yields would not reach historical norms. A key factor for not reaching previously attained yield levels is the interaction between design and manufacturing. Yield losses in the newer processes include functional defects, parametric defects and issues with testing. Each of these sources of yield loss needs to analyzed and understood by designers and tool developers. In addition, new techniques and methods must be devised to minimize the impact of these yield loss mechanisms. After an introduction of the issues involved in the first section, the second section covers Design-for-Manufacturing (DFM) techniques to analyze the design content, flag areas of design that could limit yield, and make changes to improve yield. However, once the changes are made it is necessary to quantify their impact so that knowledge about yield contribution of different features can be fed back to design and DFM tools. Test presents an opportunity to close the loop by crafting test patterns to expose the defect prone features during automatic test pattern generation (ATPG) and by analyzing silicon failures through diagnosis to determine the features that are actually causing yield loss and their relative impact. The third section covers design techniques (DFX) to improve testability, debuggability and diagnosability, and DFM and defect aware test generation to both meet product quality and expose yield issues at test. Section four covers the basic concepts and theoretical aspects of debug and diagnosis including algorithmic IC diagnosis, scan chain diagnosis, critical path based techniques and diagnosis of delay defects. The applications of the basic concepts and techniques for silicon debug are covered in section five. Section six covers the application of statistical diagnosis techniques to determine the features that are actually causing yield loss and their relative impact. Finally, in section seven, future trends, challenges and directions are covered.
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