用于高密度20v功率集成电路的自对准和屏蔽复用LDMOS

11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI:10.1109/ISPSD.1999.764060

A. Ludikhuize

{"title":"用于高密度20v功率集成电路的自对准和屏蔽复用LDMOS","authors":"A. Ludikhuize","doi":"10.1109/ISPSD.1999.764060","DOIUrl":null,"url":null,"abstract":"A self-aligned 20 V logic-level n-channel LDMOS has been integrated in a 0.6 /spl mu/m BiCMOS process, using a LATID (large angle tilted implementation drain) boron backgate implantation combined with co-implanted arsenic as a low-ohmic link under the spacer. In addition, a shielded RESURF LDMOS is reported for use as a low-side transistor in power converters, suited for 20 V in VLSI with a single thin gate oxide. This transistor suppresses parasitic injection in the substrate and uses a buried p on buried n/sup +/ layer.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"15 3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Self-aligned and shielded-RESURF LDMOS for dense 20 V power IC's\",\"authors\":\"A. Ludikhuize\",\"doi\":\"10.1109/ISPSD.1999.764060\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A self-aligned 20 V logic-level n-channel LDMOS has been integrated in a 0.6 /spl mu/m BiCMOS process, using a LATID (large angle tilted implementation drain) boron backgate implantation combined with co-implanted arsenic as a low-ohmic link under the spacer. In addition, a shielded RESURF LDMOS is reported for use as a low-side transistor in power converters, suited for 20 V in VLSI with a single thin gate oxide. This transistor suppresses parasitic injection in the substrate and uses a buried p on buried n/sup +/ layer.\",\"PeriodicalId\":352185,\"journal\":{\"name\":\"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)\",\"volume\":\"15 3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-05-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPSD.1999.764060\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.1999.764060","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 8

摘要

在0.6 /spl mu/m BiCMOS工艺中集成了一个自对准的20 V逻辑级n通道LDMOS，使用大角度倾斜实施漏极(LATID)硼后门植入，并在间隔层下共植入砷作为低欧姆链路。此外，据报道，一种屏蔽的RESURF LDMOS用于功率转换器中的低侧晶体管，适用于20 V的VLSI中使用单薄栅极氧化物。这种晶体管抑制了衬底中的寄生注入，并在埋入的n/sup +/层上使用埋入的p。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Self-aligned and shielded-RESURF LDMOS for dense 20 V power IC's

A self-aligned 20 V logic-level n-channel LDMOS has been integrated in a 0.6 /spl mu/m BiCMOS process, using a LATID (large angle tilted implementation drain) boron backgate implantation combined with co-implanted arsenic as a low-ohmic link under the spacer. In addition, a shielded RESURF LDMOS is reported for use as a low-side transistor in power converters, suited for 20 V in VLSI with a single thin gate oxide. This transistor suppresses parasitic injection in the substrate and uses a buried p on buried n/sup +/ layer.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)

自引率

0.00%

发文量