Rapid design and verification experience using flexible cycle-accurate NoC simulator

Network-on-chip (NoC) has been introduced as a novel communication interconnection structure to overcome the limitations of traditional structures in terms of bandwidth, latency, and scalability. Quick feasibility assessment of various NoC structures demands the availability of high abstraction level simulation tools. However, existing NoC simulator solutions are either too slow to address the functional simulation of real-life applications or not flexible enough to allow NoC-based design space exploration. Furthermore, the necessity to run the application tasks while observing the data-dependent traffic is often missing. In this regard, the simulation tools modeling NoC interconnection structures have to cope with various NoC parameters and allow easy modeling of applications. In addition, these tools should be cycle-accurate and provide flexibility and capability of configuration and customization. This paper addresses the requirements of NoC simulator that enable rapid design and verification of NoC-based systems. It illustrates the design experience using flexible cycle-accurate NoC simulator to implement and verify emergent applications.