基于静态NBTI老化的阈值电压提取

2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2018-10-01 DOI:10.1109/DFT.2018.8602814

Puneet Ramesh Savanur, S. Tragoudas

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引用次数: 0

摘要

提出了一种在集成电路中提取pMOS晶体管阈值电压的新方法。在给定的时间内对晶体管施加低电压，然后测量由静态负偏置温度不稳定老化引起的晶体管延迟。在45nm工艺下的实验结果表明，该方法提取阈值电压的分辨率很高。

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Threshold Voltage Extraction Using Static NBTI Aging

A novel approach to extract the threshold voltage of a pMOS transistor in a tile of the integrated circuit is proposed. Low voltage is applied to the transistor for a predetermined time period and then its delay due to static negative bias temperature instability aging is measured. Experimental results in 45nm technology show that the proposed approach extracts the threshold voltage with very high resolution.

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来源期刊

2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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