新一代介电蚀刻技术

M. Sekine
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引用次数: 1

摘要

为了在SOC(片上系统)时代开发和制造设计规则低于100纳米的器件,我们需要一种系统的工艺开发和鉴定方法。我们还需要一个定义良好的蚀刻工具,并配备监视器。它还必须有基于反应等离子体和蚀刻反应的科学理解的控制软件。该工具将使设备及其生产过程的并发开发成为可能,并具有快速的TAT(周转时间)。未来器件制造的关键问题之一是使用CF(氟碳)等离子体对ILD(层间介电材料)(如SiO/sub 2/和低k材料)的高纵横比图案蚀刻。ASET等离子体技术实验室采用了SiO/sub 2/的CF等离子体刻蚀,并开展了一项研究项目,以了解刻蚀机理,并为系统的方法、监视器和建模工具奠定基础。它在2001年3月底成功地完成了任务。本文对该项目进行了综述,并对未来的等离子体刻蚀技术进行了讨论。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Next generation dielectric etching technology
To develop and fabricate devices with a design rule below 100 nm in the SOC (System-On-a-Chip) era, we need a systematic methodology for process development and qualification. We also need an etch tool that is well-defined, and equipped with monitors. It must also have controlling software based on the scientific understanding of reactive plasma and of etch reactions. This tool will make possible the concurrent development of devices and their production processes with a quick TAT (Turn Around Time). One of the critical issues for future device manufacturing is high-aspect-ratio-pattern etching of ILD (Inter-Layer Dielectric materials), such as SiO/sub 2/ and low-k materials, using a CF (fluorocarbon) plasma. ASET Plasma Technology Laboratory adopted this CF plasma etching of SiO/sub 2/ and conducted a research project to understand the etch mechanism and to establish a basis for a systematic methodology, monitors, and modeling tools. It finished the mission successfully at the end of March 2001. This paper reviews the project and discusses about future plasma etching technologies.
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