基于不可达状态的顺序电路不可检测故障去除

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231) Pub Date : 1998-04-26 DOI:10.1109/VTEST.1998.670866

H. Yotsuyanagi, K. Kinoshita

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引用次数: 9

摘要

提出了一种基于不可达状态去除不可检测故障来减少时序电路的方法。给出了获取不可达注视点和识别可作为故障去除目标的不可检测故障的程序。给出了ISCAS基准电路的实验结果。

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Undetectable fault removal of sequential circuits based on unreachable states

We present a procedure to reduce sequential circuits by removing undetectable faults based on unreachable states. Procedures for obtaining unreachable stares and for identifying undetectable faults which can be the target of fault removal are presented. Experimental results for ISCAS benchmark circuits are shown.

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来源期刊

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)

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