{"title":"摩尔定律——还有更多吗?","authors":"K. H. Brown","doi":"10.1109/IMNC.2000.872595","DOIUrl":null,"url":null,"abstract":"Lithography improvements and device scaling have been the major driver behind the industry productivity as predicted by Moore's law over the past three decades. In fact for the past five years, in an effort to remain the productivity curve when other improvements (e.g., tool reliability, process yield) have reached their practical limits, the industry has accelerated the introduction of smaller feature sizes. Between 1994 and 1999 the technology roadmap for feature size introduction has been pulled in three years. The current timeline has features below 0.13um introduced in product by 2001. The ability to continue on this path will be dominated by two key factors at dimensions below 0.13 /spl mu/m. The first factor is the approaching limits to the scaling laws and performance benefits at the chip level. The second is cost. The author briefly reviews possible future developments in this field.","PeriodicalId":270640,"journal":{"name":"Digest of Papers Microprocesses and Nanotechnology 2000. 2000 International Microprocesses and Nanotechnology Conference (IEEE Cat. No.00EX387)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Moore's law-is there more?\",\"authors\":\"K. H. Brown\",\"doi\":\"10.1109/IMNC.2000.872595\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Lithography improvements and device scaling have been the major driver behind the industry productivity as predicted by Moore's law over the past three decades. In fact for the past five years, in an effort to remain the productivity curve when other improvements (e.g., tool reliability, process yield) have reached their practical limits, the industry has accelerated the introduction of smaller feature sizes. Between 1994 and 1999 the technology roadmap for feature size introduction has been pulled in three years. The current timeline has features below 0.13um introduced in product by 2001. The ability to continue on this path will be dominated by two key factors at dimensions below 0.13 /spl mu/m. The first factor is the approaching limits to the scaling laws and performance benefits at the chip level. The second is cost. The author briefly reviews possible future developments in this field.\",\"PeriodicalId\":270640,\"journal\":{\"name\":\"Digest of Papers Microprocesses and Nanotechnology 2000. 2000 International Microprocesses and Nanotechnology Conference (IEEE Cat. No.00EX387)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Papers Microprocesses and Nanotechnology 2000. 2000 International Microprocesses and Nanotechnology Conference (IEEE Cat. No.00EX387)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IMNC.2000.872595\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers Microprocesses and Nanotechnology 2000. 2000 International Microprocesses and Nanotechnology Conference (IEEE Cat. No.00EX387)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMNC.2000.872595","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Lithography improvements and device scaling have been the major driver behind the industry productivity as predicted by Moore's law over the past three decades. In fact for the past five years, in an effort to remain the productivity curve when other improvements (e.g., tool reliability, process yield) have reached their practical limits, the industry has accelerated the introduction of smaller feature sizes. Between 1994 and 1999 the technology roadmap for feature size introduction has been pulled in three years. The current timeline has features below 0.13um introduced in product by 2001. The ability to continue on this path will be dominated by two key factors at dimensions below 0.13 /spl mu/m. The first factor is the approaching limits to the scaling laws and performance benefits at the chip level. The second is cost. The author briefly reviews possible future developments in this field.