D. Williams, D. Adams, R. Bishop, M. Knoll, J. Murray, R. McClintock
{"title":"抗辐射64k / 256k EEPROM技术","authors":"D. Williams, D. Adams, R. Bishop, M. Knoll, J. Murray, R. McClintock","doi":"10.1109/NVMT.1996.534671","DOIUrl":null,"url":null,"abstract":"This paper summarizes the status of 64 K and 256 K radiation hardened EEPROM devices that are being produced for space and strategic applications at Northrop Grumman Corporation. These devices use Silicon-Oxide-Nitride-Oxide-Semiconductor (SONOS) technology which provides improved total dose radiation hardness over floating gate devices. Circuit design techniques provide good resistance to single event and transient radiation effects. Several CMOS/SONOS devices are being produced including an 8 K/spl times/8 EEPROM, a 32 K/spl times/8 EEPROM (in development), plus mixed mode ASICs. This technology has been demonstrated to have better than 10 year retention at 80/spl deg/C after 10/sup 4/ programming cycles. The EEPROMs utilize a radiation hardened CMOS process technology currently specified at 300 Krad(Si) total dose hardness. Both n-channel and p-channel SONOS memory transistors are currently in use, but the EEPROMs are based on n-channel SONOS.","PeriodicalId":391958,"journal":{"name":"Proceedings of Nonvolatile Memory Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Radiation hardened 64 K/256 K EEPROM technology\",\"authors\":\"D. Williams, D. Adams, R. Bishop, M. Knoll, J. Murray, R. McClintock\",\"doi\":\"10.1109/NVMT.1996.534671\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper summarizes the status of 64 K and 256 K radiation hardened EEPROM devices that are being produced for space and strategic applications at Northrop Grumman Corporation. These devices use Silicon-Oxide-Nitride-Oxide-Semiconductor (SONOS) technology which provides improved total dose radiation hardness over floating gate devices. Circuit design techniques provide good resistance to single event and transient radiation effects. Several CMOS/SONOS devices are being produced including an 8 K/spl times/8 EEPROM, a 32 K/spl times/8 EEPROM (in development), plus mixed mode ASICs. This technology has been demonstrated to have better than 10 year retention at 80/spl deg/C after 10/sup 4/ programming cycles. The EEPROMs utilize a radiation hardened CMOS process technology currently specified at 300 Krad(Si) total dose hardness. Both n-channel and p-channel SONOS memory transistors are currently in use, but the EEPROMs are based on n-channel SONOS.\",\"PeriodicalId\":391958,\"journal\":{\"name\":\"Proceedings of Nonvolatile Memory Technology Conference\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-06-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Nonvolatile Memory Technology Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NVMT.1996.534671\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Nonvolatile Memory Technology Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NVMT.1996.534671","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper summarizes the status of 64 K and 256 K radiation hardened EEPROM devices that are being produced for space and strategic applications at Northrop Grumman Corporation. These devices use Silicon-Oxide-Nitride-Oxide-Semiconductor (SONOS) technology which provides improved total dose radiation hardness over floating gate devices. Circuit design techniques provide good resistance to single event and transient radiation effects. Several CMOS/SONOS devices are being produced including an 8 K/spl times/8 EEPROM, a 32 K/spl times/8 EEPROM (in development), plus mixed mode ASICs. This technology has been demonstrated to have better than 10 year retention at 80/spl deg/C after 10/sup 4/ programming cycles. The EEPROMs utilize a radiation hardened CMOS process technology currently specified at 300 Krad(Si) total dose hardness. Both n-channel and p-channel SONOS memory transistors are currently in use, but the EEPROMs are based on n-channel SONOS.