四种多电平dram的比较仿真研究

Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 1999-08-09 DOI:10.1109/MTDT.1999.782690

G. Birk, D. Elliott, B. Cockburn

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引用次数: 15

摘要

多层DRAM (MLDRAM)试图通过每个单元记录多于1位来增加存储密度。文献中描述了几种不同的每单元2位方案;然而，由于原始论文使用的技术和操作条件不同，因此很难直接进行比较。本文提出了一项详细的仿真研究，比较了三种已发表的MLDRAM方案，以及一种新的MLDRAM方案，该方案结合了Furuyama等人(1989)提出的MLDRAM的速度和Gillingham(1996)提出的MLDRAM的降噪技术。我们的SPICE模拟模型使用相同的阵列大小和过程模型，以允许我们进行直接比较。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A comparative simulation study of four multilevel DRAMs

Multilevel DRAM (MLDRAM) attempts to increase storage density by recording more than one bit per cell. Several different two-bit-per-cell schemes have been described in the literature; however it is difficult to compare them directly because the original papers use different technologies and operating conditions. This paper presents a detailed simulation study that compares three published MLDRAM schemes, along with a new MLDRAM scheme that combines the speed of a MLDRAM proposed by Furuyama et al. (1989) and the noise cancellation techniques of a MLDRAM proposed by Gillingham (1996). Our SPICE simulation models use the same array size and process models for each to allow us to make direct comparisons.

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Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing

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