M. Qiao, Lingli Jiang, Meng Wang, Yong Huang, H. Liao, Tao Liang, Zhen Sun, Bo Zhang, Zhaoji Li, G. Huang, Yuanyuan Zhao, L. Lai, Xi Hu, Xiang Zhuang, X. Luo, Zhuo Wang
{"title":"PDP扫描驱动IC的高压厚层SOI技术","authors":"M. Qiao, Lingli Jiang, Meng Wang, Yong Huang, H. Liao, Tao Liang, Zhen Sun, Bo Zhang, Zhaoji Li, G. Huang, Yuanyuan Zhao, L. Lai, Xi Hu, Xiang Zhuang, X. Luo, Zhuo Wang","doi":"10.1109/ISPSD.2011.5890820","DOIUrl":null,"url":null,"abstract":"Based on 11-μm-thick silicon layer and 1-μm-thick buried oxide layer, a novel high-voltage thick layer SOI technology has been developed for driving plasma display panels (PDP). HV pLDMOS, nLDMOS, nLIGBT and LV CMOS are compatible with deep trench isolation. The length T, Y for HV pLDMOS and TD for HV nLDMOS are optimized to reduce the device size and satisfy the off-state breakdown voltage simultaneously. Interdigitated N+&P+ and a deep P+ are adopted in the source region of HV nLDMOS and cathode region of HV nLIGBT to suppress parasitic NPN action and gain better on-state characteristics. A PDP scan driver IC using the developed high-voltage thick layer SOI technology shows that the rise and fall times of the output stages are about 17.6 ns and 16.6 ns respectively.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"25","resultStr":"{\"title\":\"High-voltage thick layer SOI technology for PDP scan driver IC\",\"authors\":\"M. Qiao, Lingli Jiang, Meng Wang, Yong Huang, H. Liao, Tao Liang, Zhen Sun, Bo Zhang, Zhaoji Li, G. Huang, Yuanyuan Zhao, L. Lai, Xi Hu, Xiang Zhuang, X. Luo, Zhuo Wang\",\"doi\":\"10.1109/ISPSD.2011.5890820\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Based on 11-μm-thick silicon layer and 1-μm-thick buried oxide layer, a novel high-voltage thick layer SOI technology has been developed for driving plasma display panels (PDP). HV pLDMOS, nLDMOS, nLIGBT and LV CMOS are compatible with deep trench isolation. The length T, Y for HV pLDMOS and TD for HV nLDMOS are optimized to reduce the device size and satisfy the off-state breakdown voltage simultaneously. Interdigitated N+&P+ and a deep P+ are adopted in the source region of HV nLDMOS and cathode region of HV nLIGBT to suppress parasitic NPN action and gain better on-state characteristics. A PDP scan driver IC using the developed high-voltage thick layer SOI technology shows that the rise and fall times of the output stages are about 17.6 ns and 16.6 ns respectively.\",\"PeriodicalId\":132504,\"journal\":{\"name\":\"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-05-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"25\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPSD.2011.5890820\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.2011.5890820","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High-voltage thick layer SOI technology for PDP scan driver IC
Based on 11-μm-thick silicon layer and 1-μm-thick buried oxide layer, a novel high-voltage thick layer SOI technology has been developed for driving plasma display panels (PDP). HV pLDMOS, nLDMOS, nLIGBT and LV CMOS are compatible with deep trench isolation. The length T, Y for HV pLDMOS and TD for HV nLDMOS are optimized to reduce the device size and satisfy the off-state breakdown voltage simultaneously. Interdigitated N+&P+ and a deep P+ are adopted in the source region of HV nLDMOS and cathode region of HV nLIGBT to suppress parasitic NPN action and gain better on-state characteristics. A PDP scan driver IC using the developed high-voltage thick layer SOI technology shows that the rise and fall times of the output stages are about 17.6 ns and 16.6 ns respectively.
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