Design and analysis of source coupled logic circuits

In this paper, full adder circuits are implemented in pass transistor, CMOS and Source Coupled Logic and analyzed. SCL circuit is further minimized using multiplexer minimization technique and provides to an enhanced performance. Delay, power dissipation, number of transistors, current spike and their product are considered the performance metrics for the present analysis. Of the various adders implemented, SCL full adder circuit provides minimum current spike between power supply (VDD) to ground during state transition and best figure of merit. This makes SCL logic noise immune, rugged and an excellent candidate for mixed mode circuit design. Simulations are performed using Tanner EDA Tools for 0.18μm technology node.