流水线adc的设计注意事项

2016 IEEE NW Russia Young Researchers in Electrical and Electronic Engineering Conference (EIConRusNW) Pub Date : 2016-04-07 DOI:10.1109/EICONRUSNW.2016.7448266

I. Piatak, M. Pilipko, D. Morozov

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引用次数: 2

摘要

讨论了流水线模数转换器(adc)的设计注意事项。给出了流水线adc对直流增益和单位增益频率、参考电压稳定性和电容与期望SFDR失配的主要要求。给出了参考电压电路和时钟分配电路的实例，以及Cadence Virtuoso和MATLAB仿真结果。

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Design considerations for pipelined ADCs

Design considerations for pipelined analog-to-digital converters (ADCs) are discussed. The main requirements for DC gain and unity-gain frequency, reference voltage stability and capacitor mismatch versus desired SFDR of pipelined ADCs are presented. Examples of voltage reference circuits and a clock distribution circuit as well as Cadence Virtuoso and MATLAB simulation results are provided.

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2016 IEEE NW Russia Young Researchers in Electrical and Electronic Engineering Conference (EIConRusNW)

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