50G+背板链路的设计注意事项

T. Toifl, M. Braendli, A. Cevrero, P. Francese, M. Kossel, L. Kull, D. Luu, C. Menolfi, T. Morf, Ilter Özkaya, Hazar Yueksel
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引用次数: 3

摘要

不断增长的I/O带宽需求推动电背板链路达到50Gb/s及以上的数据速率。虽然电路板材料有了显著的改进,但背板链路越来越受到信号衰减的限制,同时受到ISI、抖动、器件噪声和串扰的影响。在本文中,我们总结了这些限制,并指出了可能的方向,以进一步扩大可实现的数据速率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design considerations for 50G+ backplane links
The constantly increasing need for I/O bandwidth push electrical backplane links to data rates of 50Gb/s and above. Although board materials have improved significantly, backplane links are increasingly limited by signal attenuation while suffering from ISI, jitter, device noise and cross-talk. In this paper we summarize these limitations, and show possible directions to cope with them in order to further extend the achievable data rate.
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