一个6000门CMOS门阵列

1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1982.1156281

T. Itoh, M. Takechi, M. Fujita, K. Ikuzaki, A. Masaki, M. Asano, S. Murata, S. Horiguchi, H. Yoshimura

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引用次数: 2

摘要

本文将描述一个门阵列，每个门的负载传播延迟为2ns。该器件采用2μm规则、双金属层、硅栅极技术和弯曲栅极模式，以实现最小的芯片面积。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 6,000-gate CMOS gate array

This paper will describe a gate array with a loaded propagation delay of 2ns per gate. The device employs 2μm rules, double metal layers, silicon gate technology and bent-gate patterns for a minimum chip area.

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1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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