随机分子现象的容错计算范式:Hopfield门和逻辑网络

2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI:10.1109/ISMVL.2011.21

A. H. Tran, S. Yanushkevich, S. Lyshevski, V. Shmerko

{"title":"随机分子现象的容错计算范式:Hopfield门和逻辑网络","authors":"A. H. Tran, S. Yanushkevich, S. Lyshevski, V. Shmerko","doi":"10.1109/ISMVL.2011.21","DOIUrl":null,"url":null,"abstract":"This paper contributes to robust fault-tolerant computing for expected nano-centric processing hardware. We developed (a)techniques for fault tolerant logic network design given a library of AND, OR, NAND, and NOR Hop field gates, and (b) report experimental results on fault tolerant properties of designed networks. In particular, several hundred iterations are required to achieve correct outputs in a five-input single-output networks in the presence of 40% noise.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Fault Tolerant Computing Paradigm for Random Molecular Phenomena: Hopfield Gates and Logic Networks\",\"authors\":\"A. H. Tran, S. Yanushkevich, S. Lyshevski, V. Shmerko\",\"doi\":\"10.1109/ISMVL.2011.21\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper contributes to robust fault-tolerant computing for expected nano-centric processing hardware. We developed (a)techniques for fault tolerant logic network design given a library of AND, OR, NAND, and NOR Hop field gates, and (b) report experimental results on fault tolerant properties of designed networks. In particular, several hundred iterations are required to achieve correct outputs in a five-input single-output networks in the presence of 40% noise.\",\"PeriodicalId\":234611,\"journal\":{\"name\":\"2011 41st IEEE International Symposium on Multiple-Valued Logic\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-05-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 41st IEEE International Symposium on Multiple-Valued Logic\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISMVL.2011.21\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 41st IEEE International Symposium on Multiple-Valued Logic","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.2011.21","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

本文为期望的以纳米为中心的处理硬件提供了健壮的容错计算。我们开发了(a)基于AND, OR, NAND和NOR Hop场门库的容错逻辑网络设计技术，以及(b)报告了所设计网络容错特性的实验结果。特别是，在存在40%噪声的五输入单输出网络中，需要数百次迭代才能获得正确的输出。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Fault Tolerant Computing Paradigm for Random Molecular Phenomena: Hopfield Gates and Logic Networks

This paper contributes to robust fault-tolerant computing for expected nano-centric processing hardware. We developed (a)techniques for fault tolerant logic network design given a library of AND, OR, NAND, and NOR Hop field gates, and (b) report experimental results on fault tolerant properties of designed networks. In particular, several hundred iterations are required to achieve correct outputs in a five-input single-output networks in the presence of 40% noise.

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2011 41st IEEE International Symposium on Multiple-Valued Logic

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