{"title":"基于1.8V准ecl MOS-HBT SiGe BiCMOS逻辑的108 ghz定时器","authors":"Yingying Fu, S. Voinigescu","doi":"10.1109/CSICS.2013.6659185","DOIUrl":null,"url":null,"abstract":"This paper describes the first full-rate retimer operating with clock frequencies above 100- GHz. The circuit includes a digitally-controlled equalizer with over 30 dB of peaking control at 55- 60GHz, a 108-GHz flip-flop, and a DC- to-108 GHz clock amplifier. It consumes 540 mW from a 1.8V supply corresponding to an energy efficiency of 5pJ/bit. Equalization was demonstrated over 6m of coaxial cable at 40 Gb/s and 36 Gb/s with full-rate, 2x, and 3x oversampling clocks at 80 GHz and 108 GHz, respectively, and at 75 Gb/s with 75-GHz clock between two probe stations using wafer probes and a 3-m long coaxial cable.","PeriodicalId":257256,"journal":{"name":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A 108-GHz Retimer Based on 1.8V QUASI-ECL MOS-HBT SiGe BiCMOS Logic\",\"authors\":\"Yingying Fu, S. Voinigescu\",\"doi\":\"10.1109/CSICS.2013.6659185\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the first full-rate retimer operating with clock frequencies above 100- GHz. The circuit includes a digitally-controlled equalizer with over 30 dB of peaking control at 55- 60GHz, a 108-GHz flip-flop, and a DC- to-108 GHz clock amplifier. It consumes 540 mW from a 1.8V supply corresponding to an energy efficiency of 5pJ/bit. Equalization was demonstrated over 6m of coaxial cable at 40 Gb/s and 36 Gb/s with full-rate, 2x, and 3x oversampling clocks at 80 GHz and 108 GHz, respectively, and at 75 Gb/s with 75-GHz clock between two probe stations using wafer probes and a 3-m long coaxial cable.\",\"PeriodicalId\":257256,\"journal\":{\"name\":\"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-11-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CSICS.2013.6659185\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSICS.2013.6659185","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 108-GHz Retimer Based on 1.8V QUASI-ECL MOS-HBT SiGe BiCMOS Logic
This paper describes the first full-rate retimer operating with clock frequencies above 100- GHz. The circuit includes a digitally-controlled equalizer with over 30 dB of peaking control at 55- 60GHz, a 108-GHz flip-flop, and a DC- to-108 GHz clock amplifier. It consumes 540 mW from a 1.8V supply corresponding to an energy efficiency of 5pJ/bit. Equalization was demonstrated over 6m of coaxial cable at 40 Gb/s and 36 Gb/s with full-rate, 2x, and 3x oversampling clocks at 80 GHz and 108 GHz, respectively, and at 75 Gb/s with 75-GHz clock between two probe stations using wafer probes and a 3-m long coaxial cable.
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