3.4 GB/S低延迟1位输入数字fir滤波器(0.13 μM CMOS)

2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI:10.1109/MIXDES.2007.4286146

H. Fredriksson, Christer Svensson, A. Alvandpour

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引用次数: 1

摘要

本文提出了一种用于多gb /s混合信号决策反馈均衡器的低延迟、单比特输入、高速fir滤波器。该滤波器采用了保载波FIR分接结构和高效的双向触发器复用器。该滤波器采用标准的0.13 μm CMOS技术。从提取的布局中得出的仿真结果显示，正确的功能高达3.4 G字/秒，延迟≪280 ps。

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A 3.4 GB/S Low Latency 1 Bit Input Digital FIR-Filter in 0.13 μM CMOS

This paper presents a low latency, one bit input, high-speed FIR-filter designed for multi-Gb/s mixed signal decision feedback equalizers. The filter utilizes a carry-save FIR tap structure and an efficient dual-edge-flip-flop-multiplexer. The filter has been implemented in a standard 0.13 μm CMOS technology. Simulation results from extracted layout shows correct functionality up to 3.4 G words/s with a latency ≪280 ps.

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2007 14th International Conference on Mixed Design of Integrated Circuits and Systems

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