椭圆曲线点乘法的面积感知加速器

Malik Imran, S. Pagliarini, M. Rashid
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引用次数: 5

摘要

本文提出了一种硬件加速器,在优化延迟和面积的同时,提高椭圆曲线加密中点乘法过程的性能。为了减少所提出的两阶段流水线架构的总体计算时间,在有效利用所需内存位置的同时,对点加法和点加倍指令进行了重新调度。此外,还提出了一个41位乘法器。最后给出了FPGA和ASIC的实现结果。与最先进的实现在延迟和面积方面的性能比较证明了所提出的加速器的重要性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An Area Aware Accelerator for Elliptic Curve Point Multiplication
This work presents a hardware accelerator, for the optimization of latency and area at the same time, to improve the performance of point multiplication process in Elliptic Curve Cryptography. In order to reduce the overall computation time in the proposed 2-stage pipelined architecture, a rescheduling of point addition and point doubling instructions is performed along with an efficient use of required memory locations. Furthermore, a 41-bit multiplier is also proposed. Consequently, the FPGA and ASIC implementation results have been provided. The performance comparison with state-of-the-art implementations, in terms of latency and area, proves the significance of the proposed accelerator.
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