芯片级互连、基板和封装寄生的有效建模技术

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI:10.1145/307418.307536

P. Feldmann, S. Kapur, D. Long

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引用次数: 9

摘要

现代集成电路设计需要对芯片级互连、基板和封装寄生进行精确的分析和建模。这种分析的传统方法在计算上是昂贵的。在本文中，我们讨论了一些新的提取和降阶建模方案，以帮助克服这一计算瓶颈。

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Efficient techniques for modeling chip-level interconnect, substrate and package parasitics

Modern IC design requires accurate analysis and modeling of chip-level interconnect, the substrate and package parasitics. Traditional approaches for such analyses are computationally expensive. In this paper we discuss some recent novel schemes for extraction and reduced order modeling that help overcome this computational bottleneck.

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来源期刊

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)

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