SiOC(H)低k介电材料的低损伤损伤图

Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005. Pub Date : 2005-06-06 DOI:10.1109/IITC.2005.1499913

H. Struyf, D. Hendrickx, J. Van Olmen, F. Iacopi, O. Richard, Y. Travaly, M. Van Hove, W. Boullart, S. Vanhaelemeersch

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引用次数: 6

摘要

众所周知，蚀刻和条带等离子体引起的损伤使得在damascene方案中集成敏感的低k介电体变得很麻烦。本文比较了三种基于金属硬掩模的单大马士革图像化方法。EFTEM分析和综合k值提取表明，使用基于金属硬掩模的方案，优化等离子体化学和蚀刻/条带排序，对SiOC(H)低k介电介质的损伤非常低。

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Low-damage damascene patterning of SiOC(H) low-k dielectrics

Etch and strip plasma-induced damage is well-known to make the integration of sensitive low-k dielectrics in damascene schemes cumbersome. In this paper, three metal hardmask-based single-damascene patterning approaches are compared. EFTEM analysis and integrated k-value extraction show that the use of a metal hardmask-based scheme with optimized plasma chemistries and etch/strip sequencing results in very low damage to the SiOC(H) low-k dielectric.

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Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.

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