Juan L. Aragón, D. Nicolaescu, A. Veidenbaum, A.-M. Badulescu
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Energy-efficient design for highly associative instruction caches in next-generation embedded processors
This paper proposes a low-energy solution for CAM-based highly associative I-caches using a segmented word-line and a predictor-based instruction fetch mechanism. Not all instructions in a given I-cache fetch are used due to branches. The proposed predictor determines which instructions in a cache access will be used and does not fetch any other instructions. Results show an average I-cache energy savings of 44% over the baseline case and 6% over the segmented case with no negative impact on performance.
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