{"title":"双核锁步处理器的混合在线自检策略","authors":"A. Floridia, E. Sánchez","doi":"10.1109/DFT.2018.8602982","DOIUrl":null,"url":null,"abstract":"Multi-core processors are increasingly becoming popular even in safety-critical applications, and the compliance of such systems with functional safety standards is thus mandatory. The targeted reliability figures are achieved with a combination of different solutions, in particular a largely employed one is named Dual-Core Lockstep (DCLS) configuration. In this paper, a hybrid scheme for the on-line testing of the lockstep logic is proposed, allowing for non-intrusive run-time test of lockstep comparators. The proposed solution leverages test programs developed according to the Software-Based Self-Test (SBST) approach, used in conjunction with a specialized hardware module. The effectiveness of this approach was assessed on a modified version of the OpenRISC 1200 processor, considering stuck-at faults only.","PeriodicalId":297244,"journal":{"name":"2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Hybrid On-Line Self-Test Strategy for Dual-Core Lockstep Processors\",\"authors\":\"A. Floridia, E. Sánchez\",\"doi\":\"10.1109/DFT.2018.8602982\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Multi-core processors are increasingly becoming popular even in safety-critical applications, and the compliance of such systems with functional safety standards is thus mandatory. The targeted reliability figures are achieved with a combination of different solutions, in particular a largely employed one is named Dual-Core Lockstep (DCLS) configuration. In this paper, a hybrid scheme for the on-line testing of the lockstep logic is proposed, allowing for non-intrusive run-time test of lockstep comparators. The proposed solution leverages test programs developed according to the Software-Based Self-Test (SBST) approach, used in conjunction with a specialized hardware module. The effectiveness of this approach was assessed on a modified version of the OpenRISC 1200 processor, considering stuck-at faults only.\",\"PeriodicalId\":297244,\"journal\":{\"name\":\"2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFT.2018.8602982\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFT.2018.8602982","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Hybrid On-Line Self-Test Strategy for Dual-Core Lockstep Processors
Multi-core processors are increasingly becoming popular even in safety-critical applications, and the compliance of such systems with functional safety standards is thus mandatory. The targeted reliability figures are achieved with a combination of different solutions, in particular a largely employed one is named Dual-Core Lockstep (DCLS) configuration. In this paper, a hybrid scheme for the on-line testing of the lockstep logic is proposed, allowing for non-intrusive run-time test of lockstep comparators. The proposed solution leverages test programs developed according to the Software-Based Self-Test (SBST) approach, used in conjunction with a specialized hardware module. The effectiveness of this approach was assessed on a modified version of the OpenRISC 1200 processor, considering stuck-at faults only.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
