D. Auvergne, N. Azémard, V. Bonzom, D. Deschacht, M. Robert
{"title":"CMOS电路的正式尺寸规则","authors":"D. Auvergne, N. Azémard, V. Bonzom, D. Deschacht, M. Robert","doi":"10.1109/EDAC.1991.206368","DOIUrl":null,"url":null,"abstract":"Presents a local strategy for sizing CMOS circuits. The authors show how the explicit definition of delays can be used to define delay/area optimal sizing rules. Examples are given for sizing irregular inverter arrays, NAND gates and adder cells, starting from an initial electrical netlist and ending with the fully automatically generated layout. Direct comparisons of speed/area performances are given for a linear matrix style layout implementation.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"Formal sizing rules of CMOS circuits\",\"authors\":\"D. Auvergne, N. Azémard, V. Bonzom, D. Deschacht, M. Robert\",\"doi\":\"10.1109/EDAC.1991.206368\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Presents a local strategy for sizing CMOS circuits. The authors show how the explicit definition of delays can be used to define delay/area optimal sizing rules. Examples are given for sizing irregular inverter arrays, NAND gates and adder cells, starting from an initial electrical netlist and ending with the fully automatically generated layout. Direct comparisons of speed/area performances are given for a linear matrix style layout implementation.<<ETX>>\",\"PeriodicalId\":425087,\"journal\":{\"name\":\"Proceedings of the European Conference on Design Automation.\",\"volume\":\"20 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-02-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the European Conference on Design Automation.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDAC.1991.206368\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the European Conference on Design Automation.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDAC.1991.206368","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Presents a local strategy for sizing CMOS circuits. The authors show how the explicit definition of delays can be used to define delay/area optimal sizing rules. Examples are given for sizing irregular inverter arrays, NAND gates and adder cells, starting from an initial electrical netlist and ending with the fully automatically generated layout. Direct comparisons of speed/area performances are given for a linear matrix style layout implementation.<>
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
