H. Xue, Tyler Moody, Shuo Li, Xiaomeng Zhang, S. Ren
{"title":"低开销设计,提高硬件木马检测效率","authors":"H. Xue, Tyler Moody, Shuo Li, Xiaomeng Zhang, S. Ren","doi":"10.1109/NAECON.2014.7045840","DOIUrl":null,"url":null,"abstract":"Outsourcing of IC fabrication has increased the potential for altering the genuine design with the insertion of concealed circuits (hardware Trojans). A methodology for detecting hardware Trojans (HTs) that has been pursued recently is based on comparing the power and delay response of a genuine chip to the manufactured chip/device under test (DUT). However, the probability of detecting the HT remains small in many cases due to the low probability of activating the concealed circuits. This paper proposes a technique to increase HT activity during testing by inserting probability increase circuits (PICs) at critical points in the design. Preliminary results for a standard HT example show a reduction in time for HT activation of over 95% with modest increases in power, size, and delay overhead.","PeriodicalId":318539,"journal":{"name":"NAECON 2014 - IEEE National Aerospace and Electronics Conference","volume":"288 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Low overhead design for improving hardware trojan detection efficiency\",\"authors\":\"H. Xue, Tyler Moody, Shuo Li, Xiaomeng Zhang, S. Ren\",\"doi\":\"10.1109/NAECON.2014.7045840\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Outsourcing of IC fabrication has increased the potential for altering the genuine design with the insertion of concealed circuits (hardware Trojans). A methodology for detecting hardware Trojans (HTs) that has been pursued recently is based on comparing the power and delay response of a genuine chip to the manufactured chip/device under test (DUT). However, the probability of detecting the HT remains small in many cases due to the low probability of activating the concealed circuits. This paper proposes a technique to increase HT activity during testing by inserting probability increase circuits (PICs) at critical points in the design. Preliminary results for a standard HT example show a reduction in time for HT activation of over 95% with modest increases in power, size, and delay overhead.\",\"PeriodicalId\":318539,\"journal\":{\"name\":\"NAECON 2014 - IEEE National Aerospace and Electronics Conference\",\"volume\":\"288 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-06-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"NAECON 2014 - IEEE National Aerospace and Electronics Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NAECON.2014.7045840\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"NAECON 2014 - IEEE National Aerospace and Electronics Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NAECON.2014.7045840","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Low overhead design for improving hardware trojan detection efficiency
Outsourcing of IC fabrication has increased the potential for altering the genuine design with the insertion of concealed circuits (hardware Trojans). A methodology for detecting hardware Trojans (HTs) that has been pursued recently is based on comparing the power and delay response of a genuine chip to the manufactured chip/device under test (DUT). However, the probability of detecting the HT remains small in many cases due to the low probability of activating the concealed circuits. This paper proposes a technique to increase HT activity during testing by inserting probability increase circuits (PICs) at critical points in the design. Preliminary results for a standard HT example show a reduction in time for HT activation of over 95% with modest increases in power, size, and delay overhead.